Contents
BsC in Computer Engineering and current MsC in Advanced Telecommunication Technologies student passionate about processor
design, computer architecture and open source development.
Dont’ hesitate to contact me at my email or visit my github to check out my
projects.
Academic History
Work History
Research Engineer - RTL Design - September 2026 - Present
Barcelona Supercomputing Center (BSC)
RTL Design Engineer Internship - July 2026 - September 2026
Beijing Institute of Open Source Chip (BOSC)
Implement various RISC-V vector extensions in XiangShan open source core.
Refine the implementations to meet frequency targets retaining a reasonable area budget.
RTL Design Engineer Internship - April 2025 - Present
Barcelona Supercomputing Center (BSC)
Implement various RISC-V extension to accomplish RVA23 in an open source core.
Make decisions based on power, performance and area metrics to choose the most suitable option.
Benchmark the impact of the modifications both in simulation and on FPGA.
Support college teaching - 2023 - 2024
Universitat Politècnica de Catalunya (UPC)
Prepare university level classes aimed towards students with
difficulties with the subject.
Decomposition of complex topics into bite-size lectures to make sure
the students understood and learnt the curriculum.
Highschool tutor - 2021 - 2023
Self-employed
Highschool classes in Math, Programming (Python and C++), Physics,
Electrical Engineering, Industrial Technology and Technical
Drawing.
Skills
Programming Languages : SystemVerilog, C/C++, Python (Flask), SQL,
JavascriptHardware skills: RISC-V, UVM, Arduino, Raspberry Pi, PIC,
AssamblyLanguages : English (C1), Spanish(Native), French
(B1), Catalan (Native)
Current Projects
RISC-V
Processor : A simple, single cycle Risc V processor written in System
Verilog. With the future intention to test it in a FPGA.